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<p>This paper introduces a race-free cascaded dynamic positive feedback source-coupled logic (Dy-PFSCL) circuit, derived from NORA dynamic CMOS. Traditional Dy-PFSCL gates suffer from erroneous evaluation problem between stages during cascading, typically requiring intermediary circuits such as inverters or buffers that use clock delay or self-timing mechanisms. This work presents a novel, complementary (P-type) Dy-PFSCL inverter design that achieves a race-free, NORA-based cascaded (n-type and p-type stages) configuration without requiring intermediary circuits, making it immune to overlapping clock signals. The proposed design reduces power dissipation, delay, power-delay product (PDP), and area, as validated through simulations using GPDK 45&#xa0;nm CMOS technology with a 1.1&#xa0;V supply voltage in Cadence Virtuoso. Results show maximum improvements of 54.44% in delay, 35.36% in power consumption, 70.58% in PDP, and 28.52% in area over existing techniques. These performance improvements are confirmed with post-layout simulations, while robustness is further verified under Monte Carlo analysis and PVT (process-voltage-temperature) variations, proving the proposed rece-free Dy-PFSCL to be more effective in performance and efficiency than existing circuit. A full-adder circuit is designed using the proposed race-free Dy-PFSCL cascading method and is compared with a conventional Dy-PFSCL design that uses self-timed buffers. The proposed approach shows improved performance due to its simpler structure and reduced hardware components.</p>

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Improved Race-Free Cascaded Dynamic PFSCL Technique for Multistage Applications

  • 期刊论文

  • 发表日期：

    2026年2月4日

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  • Dheeraj Singh Rajput,
  • Bharat Choudhary,
  • Dharmendar Boolchandani,
  • Archana Singhal

摘要

This paper introduces a race-free cascaded dynamic positive feedback source-coupled logic (Dy-PFSCL) circuit, derived from NORA dynamic CMOS. Traditional Dy-PFSCL gates suffer from erroneous evaluation problem between stages during cascading, typically requiring intermediary circuits such as inverters or buffers that use clock delay or self-timing mechanisms. This work presents a novel, complementary (P-type) Dy-PFSCL inverter design that achieves a race-free, NORA-based cascaded (n-type and p-type stages) configuration without requiring intermediary circuits, making it immune to overlapping clock signals. The proposed design reduces power dissipation, delay, power-delay product (PDP), and area, as validated through simulations using GPDK 45 nm CMOS technology with a 1.1 V supply voltage in Cadence Virtuoso. Results show maximum improvements of 54.44% in delay, 35.36% in power consumption, 70.58% in PDP, and 28.52% in area over existing techniques. These performance improvements are confirmed with post-layout simulations, while robustness is further verified under Monte Carlo analysis and PVT (process-voltage-temperature) variations, proving the proposed rece-free Dy-PFSCL to be more effective in performance and efficiency than existing circuit. A full-adder circuit is designed using the proposed race-free Dy-PFSCL cascading method and is compared with a conventional Dy-PFSCL design that uses self-timed buffers. The proposed approach shows improved performance due to its simpler structure and reduced hardware components.