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<p>Reliability in Integrated Circuit (IC) design is increasingly dependent on fault detection procedures in the pre-silicon stage as the complexity and scope of Very Large Scale Integration (VLSI) designs increase. By turning most fault detection algorithms into satisfiability (SAT) problems that SAT solvers can understand, the algorithms can be solved. But SAT solvers require a lot of processing power time, due to the issue of the search space explosion. In this paper, an Automated Debugging of Design Errors using Optimized Multi-Component Attention Graph Convolutional Neural Network in Digital VLSI Circuits (ADDE-MCAGCNN-VLSI) is proposed. Initially, input data collected from C17 Circuit using ATLANTA Tool is used. Then, the input data is fed into feature extraction stage using High-order Time-reassigned Synchro squeezing Transform (HTSST) to extract the dimension reduction from the data. Afterwards, the extracted features are given to the Multi-Component Attention Graph Convolutional Neural Network (MCAGCNN) for detecting the fault on automated debugging of design errors in digital VLSI circuits. Finally, Snow Ablation Optimizer (SAO) is proposed in this work to optimize the weight parameter of ADDE-MCAGCNN-VLSI classifier, which precisely detects the fault in digital VLSI circuits. The proposed approach achieves an efficiency improvement of 99% in fault detection in digital VLSI circuits accuracy compared to the existing methods. The proposed ADDE-MCAGCNN-VLSI method is implemented and examined under performance metrics, such as Debugging Accuracy, Validation Accuracy, Debugging Coverage, latency, Resource utilization, Error localization, False Positive Rate and false Negative Rate are evaluated. Experimental evaluation on the C17 dataset demonstrates that the ADDE-MCAGCNN-VLSI achieves a fault detection accuracy of 99.57%, representing an absolute improvement of 16–31% over existing methods such as ADED-VLSI, VLSI-VHDL-AI and VLSI-EDC-SS. The model also achieves up to 24–32% lower error localization.</p>

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Automated Debugging of Design Errors using Optimized Multi-Component Attention Graph Convolutional Neural Network in Digital VLSI Circuits

  • 期刊论文

  • 发表日期：

    2026年2月9日

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  • Neeraj Kumar Shukla

摘要

Reliability in Integrated Circuit (IC) design is increasingly dependent on fault detection procedures in the pre-silicon stage as the complexity and scope of Very Large Scale Integration (VLSI) designs increase. By turning most fault detection algorithms into satisfiability (SAT) problems that SAT solvers can understand, the algorithms can be solved. But SAT solvers require a lot of processing power time, due to the issue of the search space explosion. In this paper, an Automated Debugging of Design Errors using Optimized Multi-Component Attention Graph Convolutional Neural Network in Digital VLSI Circuits (ADDE-MCAGCNN-VLSI) is proposed. Initially, input data collected from C17 Circuit using ATLANTA Tool is used. Then, the input data is fed into feature extraction stage using High-order Time-reassigned Synchro squeezing Transform (HTSST) to extract the dimension reduction from the data. Afterwards, the extracted features are given to the Multi-Component Attention Graph Convolutional Neural Network (MCAGCNN) for detecting the fault on automated debugging of design errors in digital VLSI circuits. Finally, Snow Ablation Optimizer (SAO) is proposed in this work to optimize the weight parameter of ADDE-MCAGCNN-VLSI classifier, which precisely detects the fault in digital VLSI circuits. The proposed approach achieves an efficiency improvement of 99% in fault detection in digital VLSI circuits accuracy compared to the existing methods. The proposed ADDE-MCAGCNN-VLSI method is implemented and examined under performance metrics, such as Debugging Accuracy, Validation Accuracy, Debugging Coverage, latency, Resource utilization, Error localization, False Positive Rate and false Negative Rate are evaluated. Experimental evaluation on the C17 dataset demonstrates that the ADDE-MCAGCNN-VLSI achieves a fault detection accuracy of 99.57%, representing an absolute improvement of 16–31% over existing methods such as ADED-VLSI, VLSI-VHDL-AI and VLSI-EDC-SS. The model also achieves up to 24–32% lower error localization.