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<p>This paper presents a compact, high-speed pseudorandom binary sequence (PRBS) generator designed for embedded testing in high-speed communication systems. The proposed design optimizes performance using an improved 8-transistor true single-phase clock D-type flip-flop (DFF) and a compact 6-transistor transmission-gate-based XOR gate. It reduces the area compared to conventional linear feedback shift register implementations. A retiming DFF is strategically included to enhance signal integrity. Fabricated in 0.18-μm complementary metal–oxide–semiconductor technology, the core occupies an area of 148.3&#xa0;μm × 24.6&#xa0;μm. Post-layout simulations with complete parasitic extraction reveal a maximum stable operating frequency of 3&#xa0;GHz; however, the system can still generate sequence signals at 4&#xa0;GHz, albeit with reduced signal integrity. Experimental verification confirms reliable 3&#xa0;Gb/s operation, exhibiting 30.8&#xa0;ps timing jitter, mainly due to additional random jitter, PCB parasitics, and clock source imperfections that are not present in simulations. The PRBS generator chip consumes 19 mW, demonstrating its low power consumption. The results validate the architecture’s suitability for high-speed, low-power, and compact integrated testing solutions.</p>

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A Low-Power 3-Gb/s PRBS Generator Using an Improved TSPC D-Type Flip-Flop in 0.18 µm CMOS Technology

  • 期刊论文

  • 发表日期：

    2026年2月4日

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  • Jau-Ji Jou,
  • Po-Yen Wang,
  • Wahyu Hidayat,
  • Bo-Hong Liu,
  • Chun-Liang Yang,
  • Chih-Lung Tseng

摘要

This paper presents a compact, high-speed pseudorandom binary sequence (PRBS) generator designed for embedded testing in high-speed communication systems. The proposed design optimizes performance using an improved 8-transistor true single-phase clock D-type flip-flop (DFF) and a compact 6-transistor transmission-gate-based XOR gate. It reduces the area compared to conventional linear feedback shift register implementations. A retiming DFF is strategically included to enhance signal integrity. Fabricated in 0.18-μm complementary metal–oxide–semiconductor technology, the core occupies an area of 148.3 μm × 24.6 μm. Post-layout simulations with complete parasitic extraction reveal a maximum stable operating frequency of 3 GHz; however, the system can still generate sequence signals at 4 GHz, albeit with reduced signal integrity. Experimental verification confirms reliable 3 Gb/s operation, exhibiting 30.8 ps timing jitter, mainly due to additional random jitter, PCB parasitics, and clock source imperfections that are not present in simulations. The PRBS generator chip consumes 19 mW, demonstrating its low power consumption. The results validate the architecture’s suitability for high-speed, low-power, and compact integrated testing solutions.