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<p>A 0.5 V 10-bit 500 KS/s successive approximation register analog-to-digital converters (SAR ADC) with energy-efficiency switching scheme and low-noise comparator is proposed. The proposed switching scheme for switching two digital-to-analog converters (DACs) can achieve double input signal processing compared to other schemes, allowing half of the reference voltage to process the same input signal, thereby effectively reducing power consumption. The results of the Matlab simulation show that the proposed scheme achieves a 99.9% power reduction and a 93% area savings over the conventional switching scheme. Additionally, the comparator adopts a floating inverter amplifier as the preamplifier stage to provide higher gain under 0.5V supply, suppress kickback noise and reduce the input common-mode voltage on the comparator performance. The architecture aims to increase the gain of the preamplifier, thereby achieving lower noise. The proposed SAR ADC is designed in 65-nm CMOS technology, achieving a signal-to-noise and distortion ratio of 58.56 dB, a spurious-free dynamic range of 71.88 dB, with a power consumption of 2.996 uW and occupping an area of 0.052 <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\hbox {mm}^2\)</EquationSource> </InlineEquation>, resulting in Walden and Schreier’s FoM are 8.58 fJ/conversionstep and 167.83 dB, respectively.</p>

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A 0.5 V 10-bit 500 KS/s SAR ADC with Energy-Efficiency Switching Scheme and Low-Noise Comparator

  • 期刊论文

  • 发表日期：

    2026年2月9日

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  • Xue Cui,
  • Dawei Dong,
  • Zhenrong Li,
  • Liyan Yu

摘要

A 0.5 V 10-bit 500 KS/s successive approximation register analog-to-digital converters (SAR ADC) with energy-efficiency switching scheme and low-noise comparator is proposed. The proposed switching scheme for switching two digital-to-analog converters (DACs) can achieve double input signal processing compared to other schemes, allowing half of the reference voltage to process the same input signal, thereby effectively reducing power consumption. The results of the Matlab simulation show that the proposed scheme achieves a 99.9% power reduction and a 93% area savings over the conventional switching scheme. Additionally, the comparator adopts a floating inverter amplifier as the preamplifier stage to provide higher gain under 0.5V supply, suppress kickback noise and reduce the input common-mode voltage on the comparator performance. The architecture aims to increase the gain of the preamplifier, thereby achieving lower noise. The proposed SAR ADC is designed in 65-nm CMOS technology, achieving a signal-to-noise and distortion ratio of 58.56 dB, a spurious-free dynamic range of 71.88 dB, with a power consumption of 2.996 uW and occupping an area of 0.052 \(\hbox {mm}^2\) , resulting in Walden and Schreier’s FoM are 8.58 fJ/conversionstep and 167.83 dB, respectively.