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<p>This paper presents a new design of memtranstor emulator using operational transconductance amplifier, voltage differencing differential input buffered amplifier, dual-output second-generation current conveyor (DO-CCII), and three grounded capacitors. The fingerprints of memtranstor have been obtained on LTspice using 180&#xa0;nm CMOS technology parameters. The pinched hysteresis loops have been obtained for different ranges of frequencies. The inclined pinched hysteresis loops and butterfly responses have been achieved by varying the DC voltage. The transient analysis and Monte Carlo analysis have also been obtained for the proposed memtranstor emulator. The custom layout of proposed memtranstor emulator has been developed. The proposed design of memtranstor emulator has also been verified through the macro models of available ICs on SPICE. Further, the experimental results have been validated through hardware implementation of proposed memtranstor emulator using LM13700, AD830, AD633, and AD844 ICs. The obtained results clearly indicate the workability of proposed design of memtranstor emulator. The performance of proposed memtranstor emulator has also been verified through its application in chaotic circuit and synaptic plasticity.</p>

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New Design of Memtranstor Emulator and Its Application

  • 期刊论文

  • 发表日期：

    2026年1月28日

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  • Bhawna Aggarwal,
  • Shireesh Kumar Rai,
  • Rupam Das,
  • Ashish Kumar Rai

摘要

This paper presents a new design of memtranstor emulator using operational transconductance amplifier, voltage differencing differential input buffered amplifier, dual-output second-generation current conveyor (DO-CCII), and three grounded capacitors. The fingerprints of memtranstor have been obtained on LTspice using 180 nm CMOS technology parameters. The pinched hysteresis loops have been obtained for different ranges of frequencies. The inclined pinched hysteresis loops and butterfly responses have been achieved by varying the DC voltage. The transient analysis and Monte Carlo analysis have also been obtained for the proposed memtranstor emulator. The custom layout of proposed memtranstor emulator has been developed. The proposed design of memtranstor emulator has also been verified through the macro models of available ICs on SPICE. Further, the experimental results have been validated through hardware implementation of proposed memtranstor emulator using LM13700, AD830, AD633, and AD844 ICs. The obtained results clearly indicate the workability of proposed design of memtranstor emulator. The performance of proposed memtranstor emulator has also been verified through its application in chaotic circuit and synaptic plasticity.