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<p>Functional link adaptive filters (FLAF) belong to a class of nonlinear adaptive filters which are proven to perform better than traditional linear adaptive filters in various practical applications including acoustic echo cancellation, and active noise control. However, the superior modelling capability of FLAF comes at the expense of high computational complexity, which poses several hardware implementation challenges. At the algorithm level the Hammerstein block-oriented FLAF (HBO-FLAF) solves the complexity problem by splitting the FLAF filter into two small cascade filters. But still several hardware implementation challenges persist. To address this issue, this paper proposes a series of algorithmic reformulations and architectural optimizations to reduce computational complexity and improve the accuracy of the FLAF and the HBO-FLAF algorithm. We exploit the unique structure of trigonometric FLAFs and present area-efficient architectures that combine the logarithmic number system with efficient look-up tables in an innovative manner. ASIC synthesis results in 45-nm technology reveal that the proposed reformulated architectures achieve significant improvements in area and power efficiency compared to state-of-the-art architectures and higher throughput rates than other area-efficient architectures.</p>

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High-Throughput and Area-Efficient VLSI Architectures for Functional Link Adaptive Filters

  • 期刊论文

  • 发表日期：

    2025年12月9日

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  • Pavankumar Ganjimala,
  • Vinay Chakravarthi Gogineni,
  • Subrahmanyam Mula

摘要

Functional link adaptive filters (FLAF) belong to a class of nonlinear adaptive filters which are proven to perform better than traditional linear adaptive filters in various practical applications including acoustic echo cancellation, and active noise control. However, the superior modelling capability of FLAF comes at the expense of high computational complexity, which poses several hardware implementation challenges. At the algorithm level the Hammerstein block-oriented FLAF (HBO-FLAF) solves the complexity problem by splitting the FLAF filter into two small cascade filters. But still several hardware implementation challenges persist. To address this issue, this paper proposes a series of algorithmic reformulations and architectural optimizations to reduce computational complexity and improve the accuracy of the FLAF and the HBO-FLAF algorithm. We exploit the unique structure of trigonometric FLAFs and present area-efficient architectures that combine the logarithmic number system with efficient look-up tables in an innovative manner. ASIC synthesis results in 45-nm technology reveal that the proposed reformulated architectures achieve significant improvements in area and power efficiency compared to state-of-the-art architectures and higher throughput rates than other area-efficient architectures.