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<p>In this article, a novel circuit-level architecture for phase-frequency detector (PFD) implementation is presented. A key feature of the proposed PFD circuit, compared to previous PFD designs, is that once an initial input reaches a high level and the corresponding output is activated, any subsequent input that reaches a high level after a delay will no longer activate its output. Instead, it is immediately set to zero due to the activation of the initial output. Consequently, in this architecture, the two outputs are never activated simultaneously, thereby eliminating the requirement for a reset path. As a result, the reset delay, T<sub>reset</sub>, is zero. T<sub>reset</sub> is a critical factor influencing the values of both the dead zone and blind zone parameters. As a result of T<sub>reset</sub> being zero, both the dead zone and blind zone values are also zero. The proposed circuit provides several key advantages, including a reduced transistor count, low power consumption, a wide operating frequency range, and improved performance by achieving zero dead zone and blind zone. The proposed PFD was implemented using the TSMC 65&#xa0;nm CMOS technology library with a supply voltage of 1.2&#xa0;V. Its performance was thoroughly evaluated using HSPICE simulations. The simulation results demonstrate an operating frequency of 7&#xa0;GHz and a power consumption of 57&#xa0;µW. Furthermore, the dead zone and blind zone values for the proposed PFD circuit are both zero.</p>

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A New High Speed, Low Power, Zero Blind Zone, and Zero Dead Zone PFD

  • 期刊论文

  • 发表日期：

    2025年11月27日

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  • Zahra Hejabri,
  • Amir Fathi,
  • Mir Majid Ghasemi,
  • Alireza Abolhasani

摘要

In this article, a novel circuit-level architecture for phase-frequency detector (PFD) implementation is presented. A key feature of the proposed PFD circuit, compared to previous PFD designs, is that once an initial input reaches a high level and the corresponding output is activated, any subsequent input that reaches a high level after a delay will no longer activate its output. Instead, it is immediately set to zero due to the activation of the initial output. Consequently, in this architecture, the two outputs are never activated simultaneously, thereby eliminating the requirement for a reset path. As a result, the reset delay, Treset, is zero. Treset is a critical factor influencing the values of both the dead zone and blind zone parameters. As a result of Treset being zero, both the dead zone and blind zone values are also zero. The proposed circuit provides several key advantages, including a reduced transistor count, low power consumption, a wide operating frequency range, and improved performance by achieving zero dead zone and blind zone. The proposed PFD was implemented using the TSMC 65 nm CMOS technology library with a supply voltage of 1.2 V. Its performance was thoroughly evaluated using HSPICE simulations. The simulation results demonstrate an operating frequency of 7 GHz and a power consumption of 57 µW. Furthermore, the dead zone and blind zone values for the proposed PFD circuit are both zero.