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<p>In this work two feedforward current mode DC electrode offset (DEO) cancellation schemes for a bio-potential acquisition system are presented. These two schemes are applied to a modified transconduactance (TC)-transimpedance (TI) based instrumentation amplifier. The proposed configurations use two low-pass filters, first one in voltage mode and the second one in current mode. The first configuration removes ± 100 mV of DC offset, whereas the second configuration is able to cancel ± 120 mV of offset. These two configurations consume less power, 9.7 <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\mu\)</EquationSource> </InlineEquation>W and 4.1 <InlineEquation ID="IEq4"> <EquationSource Format="TEX">\(\mu\)</EquationSource> </InlineEquation>W respectively, compared to most of the previous configurations. Moreover, the capacitance requirement to realize the bandpass characteristics of the complete acquisition system is much less compared to others. Both the configurations are designed and simulated in UMC 180nm CMOS process. Post-layout simulations are also carried out and the results are presented along with the simulation results.</p>

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Bio-potential Acquisition System with Current Mode DC Electrode Offset Cancellation

  • 期刊论文

  • 发表日期：

    2025年11月16日

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  • Apurbaranjan Panda,
  • Sougata Kumar Kar

摘要

In this work two feedforward current mode DC electrode offset (DEO) cancellation schemes for a bio-potential acquisition system are presented. These two schemes are applied to a modified transconduactance (TC)-transimpedance (TI) based instrumentation amplifier. The proposed configurations use two low-pass filters, first one in voltage mode and the second one in current mode. The first configuration removes ± 100 mV of DC offset, whereas the second configuration is able to cancel ± 120 mV of offset. These two configurations consume less power, 9.7 \(\mu\) W and 4.1 \(\mu\) W respectively, compared to most of the previous configurations. Moreover, the capacitance requirement to realize the bandpass characteristics of the complete acquisition system is much less compared to others. Both the configurations are designed and simulated in UMC 180nm CMOS process. Post-layout simulations are also carried out and the results are presented along with the simulation results.