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<p>Approximate computing techniques have gathered the attention of researchers in the past decade for hardware implementation of error-resilient information processing algorithms. Using approximate computing, one can optimize power consumption and reduce chip area by utilizing less accurate functions implemented using fewer digital logic gates. However, to the best of our knowledge, these techniques have not been explored much in the design of circuitry for biomedical signal processing. Irrespective of the application, low-pass digital filters play an indispensable role in the hardware implementation of biomedical signal acquisition systems. A major challenge in optimizing the power and area requirements of such filters lies in the efficient design of its two constituent circuits, viz. adders and multipliers. This paper proposes a novel approximate computing based Vedic multiplier architecture, which has been used in the design of the proposed low-pass digital filter. Through extensive experimentation by considering biomedical signal records from physiological signal databases, it has been demonstrated that the proposed low-pass digital filter is efficient in removing high-frequency noise while consuming lower area and power dissipation than contemporary architectures proposed in the literature. The RTL-to-GDSII flow was completed using Cadence’s digital design and sign-off tools for SCL CMOS 180 nm technology. The results indicate that the proposed filter architecture occupies 50.8% lower area and 14.7% lower power consumption than the state-of-the-art designs described in the literature.</p>

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Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition

  • 期刊论文

  • 发表日期：

    2025年11月11日

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  • Sudhanshu Janwadkar,
  • Rasika Dhavse

摘要

Approximate computing techniques have gathered the attention of researchers in the past decade for hardware implementation of error-resilient information processing algorithms. Using approximate computing, one can optimize power consumption and reduce chip area by utilizing less accurate functions implemented using fewer digital logic gates. However, to the best of our knowledge, these techniques have not been explored much in the design of circuitry for biomedical signal processing. Irrespective of the application, low-pass digital filters play an indispensable role in the hardware implementation of biomedical signal acquisition systems. A major challenge in optimizing the power and area requirements of such filters lies in the efficient design of its two constituent circuits, viz. adders and multipliers. This paper proposes a novel approximate computing based Vedic multiplier architecture, which has been used in the design of the proposed low-pass digital filter. Through extensive experimentation by considering biomedical signal records from physiological signal databases, it has been demonstrated that the proposed low-pass digital filter is efficient in removing high-frequency noise while consuming lower area and power dissipation than contemporary architectures proposed in the literature. The RTL-to-GDSII flow was completed using Cadence’s digital design and sign-off tools for SCL CMOS 180 nm technology. The results indicate that the proposed filter architecture occupies 50.8% lower area and 14.7% lower power consumption than the state-of-the-art designs described in the literature.