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<p>Power estimation and minimization are inherent problems in VLSI CMOS circuit design, especially for signal processing applications such as Variable Digital Filters (VDFs), which demand high performance and low energy consumption. This work proposes an energy-efficient VLSI design for variable digital filtering by utilizing all-pass transformation (APT) techniques in combination with specially designed low-power approximate computing units: a floating-point adder (LP-AFPA) and a compressor-based multiplier (LP-CAM). These modules are made in such a way that they consume dynamic power by minimizing switching activity and logic depth. Power estimation, performed by Xilinx ISE 14.5 with an operating frequency of 210.87&#xa0;MHz, shows remarkable improvements: the new architecture consumes up to 38.9% less power. It has 11.9% less delay compared to traditional approaches. The VLSI filter proposed herein was also extremely computationally accurate with 92% accuracy, 0.08 MAE, and 27.17&#xa0;dB PSNR while still holding computational complexity of O(n). These observations corroborate the usability of approximation methods in reducing the power consumption of VLSI CMOS technology indicating that the approach proposed is exceedingly appropriate for implementing next-generation low-power digital filters.</p>

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Low-Power Design and Estimation of VLSI CMOS Architectures Using approximate Arithmetic for Digital Filter Applications

  • 期刊论文

  • 发表日期：

    2025年12月29日

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  • C. Arun Prasath,
  • C. Gowri Shankar

摘要

Power estimation and minimization are inherent problems in VLSI CMOS circuit design, especially for signal processing applications such as Variable Digital Filters (VDFs), which demand high performance and low energy consumption. This work proposes an energy-efficient VLSI design for variable digital filtering by utilizing all-pass transformation (APT) techniques in combination with specially designed low-power approximate computing units: a floating-point adder (LP-AFPA) and a compressor-based multiplier (LP-CAM). These modules are made in such a way that they consume dynamic power by minimizing switching activity and logic depth. Power estimation, performed by Xilinx ISE 14.5 with an operating frequency of 210.87 MHz, shows remarkable improvements: the new architecture consumes up to 38.9% less power. It has 11.9% less delay compared to traditional approaches. The VLSI filter proposed herein was also extremely computationally accurate with 92% accuracy, 0.08 MAE, and 27.17 dB PSNR while still holding computational complexity of O(n). These observations corroborate the usability of approximation methods in reducing the power consumption of VLSI CMOS technology indicating that the approach proposed is exceedingly appropriate for implementing next-generation low-power digital filters.