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<p>A grounded meminductor emulator (MIE) with only five metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed. Out of the five MOSFETs, three NMOS transistors and two PMOS transistors is proposed. The architecture uses an active gyrator topology in which one MOSFET (NMOS), which serves as a MOS capacitor, displays memory behavior and inductive properties as well. The MOS capacitor in the circuit eliminates the need for passive components. Its performance robustness has been validated through extensive analysis such as non-volatility test, thermal stability, tunability, Monte Carlo simulations, and process corner evaluations. Simulations are conducted using 90 nm GPDK CMOS technology on the Cadence Virtuoso Spectre (CVS) tool. The proposed design achieves a static power consumption of 2.52 mW, dynamic power of 3.23 mW (at ± 0.8V, <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(27^\circ \textrm{C}\)</EquationSource> </InlineEquation>, 0.2 <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(V_{pp}\)</EquationSource> </InlineEquation>, &amp; 100 KHz), and a silicon area of 80.5 <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\mu m^2\)</EquationSource> </InlineEquation>. It maintains stable operation up to 200 MHz and has been validated experimentally up to 850 kHz using ALD1116/1117 MOSFET arrays. The divergence between simulated (200 MHz) and experimental (850 kHz) bandwidths is attributed to discrete-prototype non-idealities: higher device capacitances in ALD arrays, SOIC lead parasitics, breadboard wiring capacitance, and measurement loading. Practical implementations in adaptive learning systems and chaotic oscillator circuit further demonstrate its applicability in well-known nonlinear circuits. A comparative assessment with existing meminductor emulators highlight the proposed meminductor emulator’s superior efficiency and compactness.</p>

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MOSFET-Meminductor Emulator Circuit with Experimental Validation and Application in Adaptive Learning and Chua’s Oscillator Circuit

  • 期刊论文

  • 发表日期：

    2025年10月14日

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  • Rahul Kumar Gupta,
  • Varun Saxena,
  • Mahipal Singh Choudhry

摘要

A grounded meminductor emulator (MIE) with only five metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed. Out of the five MOSFETs, three NMOS transistors and two PMOS transistors is proposed. The architecture uses an active gyrator topology in which one MOSFET (NMOS), which serves as a MOS capacitor, displays memory behavior and inductive properties as well. The MOS capacitor in the circuit eliminates the need for passive components. Its performance robustness has been validated through extensive analysis such as non-volatility test, thermal stability, tunability, Monte Carlo simulations, and process corner evaluations. Simulations are conducted using 90 nm GPDK CMOS technology on the Cadence Virtuoso Spectre (CVS) tool. The proposed design achieves a static power consumption of 2.52 mW, dynamic power of 3.23 mW (at ± 0.8V, \(27^\circ \textrm{C}\) , 0.2 \(V_{pp}\) , & 100 KHz), and a silicon area of 80.5 \(\mu m^2\) . It maintains stable operation up to 200 MHz and has been validated experimentally up to 850 kHz using ALD1116/1117 MOSFET arrays. The divergence between simulated (200 MHz) and experimental (850 kHz) bandwidths is attributed to discrete-prototype non-idealities: higher device capacitances in ALD arrays, SOIC lead parasitics, breadboard wiring capacitance, and measurement loading. Practical implementations in adaptive learning systems and chaotic oscillator circuit further demonstrate its applicability in well-known nonlinear circuits. A comparative assessment with existing meminductor emulators highlight the proposed meminductor emulator’s superior efficiency and compactness.