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<p>This paper presents an ultra-low noise, low-power cascoded double-tail (CDT) dynamic comparator designed for high-resolution analog-to-digital converters (ADCs). The enhanced noise performance is achieved by employing a high-gain cascoded dynamic amplifier (DA), while low power consumption is maintained through dynamic biasing without compromising gain or noise. Analytical expressions for the DA’s gain and input-referred noise are derived and validated by simulation, revealing that parasitic capacitances primarily govern the gain. Accordingly, careful transistor sizing is applied to optimize noise performance and energy efficiency. Implemented in a 130<i>nm</i> UMC CMOS process, the proposed comparator achieves an input-referred noise of <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(214\mu V\)</EquationSource> </InlineEquation>, an offset voltage of 4.29<i>mV</i>, and a power consumption of just <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(44\mu W\)</EquationSource> </InlineEquation> at 1.2<i>V</i> and 500<i>MHz</i>. Compared to recent works, the noise performance improves by at least 2<InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\times\)</EquationSource> </InlineEquation>. Two figures of merit are used to benchmark the design against state-of-the-art comparators. While optimized for low-noise, low-power ADCs in submicron CMOS technologies, the architecture remains flexible and can support higher-speed ADCs with minor trade-offs in noise and resolution to enhance energy efficiency.</p>

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An Ultra-Low Noise Dynamic Comparator for Low-Power, High-Resolution SAR ADCs

  • 期刊论文

  • 发表日期：

    2025年11月15日

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  • Amr M. Maghraby,
  • Hesham N. Ahmed,
  • Islam T. Abougindia

摘要

This paper presents an ultra-low noise, low-power cascoded double-tail (CDT) dynamic comparator designed for high-resolution analog-to-digital converters (ADCs). The enhanced noise performance is achieved by employing a high-gain cascoded dynamic amplifier (DA), while low power consumption is maintained through dynamic biasing without compromising gain or noise. Analytical expressions for the DA’s gain and input-referred noise are derived and validated by simulation, revealing that parasitic capacitances primarily govern the gain. Accordingly, careful transistor sizing is applied to optimize noise performance and energy efficiency. Implemented in a 130nm UMC CMOS process, the proposed comparator achieves an input-referred noise of \(214\mu V\) , an offset voltage of 4.29mV, and a power consumption of just \(44\mu W\) at 1.2V and 500MHz. Compared to recent works, the noise performance improves by at least 2 \(\times\) . Two figures of merit are used to benchmark the design against state-of-the-art comparators. While optimized for low-noise, low-power ADCs in submicron CMOS technologies, the architecture remains flexible and can support higher-speed ADCs with minor trade-offs in noise and resolution to enhance energy efficiency.