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<p>This paper proposes a novel <i>n</i>th-order memristor emulator circuit that employs operational transconductance amplifiers (OTAs), grounded capacitors and a single NMOS transistor. Unlike traditional emulators, which are limited to first-order behavior, the presented design realizes higher-order memristive characteristics electronically by cascading integrator stages. This approach offers a practical way to investigate the complex memory effects that are crucial for advanced computational models and difficult to achieve with physical devices or first-order emulators. The emulator is fully resistorless and offers electronic tunability via OTA bias currents, providing memductance control. The circuit was implemented using 0.18&#xa0;μm CMOS technology and validated through PSPICE simulations. The results demonstrate characteristic pinched hysteresis loops (PHLs) that vary with frequency, confirming the circuit’s memristive nature. The emulator supports both incremental and decremental configurations, exhibiting robust performance under Monte Carlo and temperature variation analyses.</p>

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Design and Simulation of a High-Order Memristor Emulator Based on Cascaded OTA Integrators

  • 期刊论文

  • 发表日期：

    2025年10月5日

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  • Mehmet Sagbas,
  • Shahram Minaei,
  • Muzaffer Çayir

摘要

This paper proposes a novel nth-order memristor emulator circuit that employs operational transconductance amplifiers (OTAs), grounded capacitors and a single NMOS transistor. Unlike traditional emulators, which are limited to first-order behavior, the presented design realizes higher-order memristive characteristics electronically by cascading integrator stages. This approach offers a practical way to investigate the complex memory effects that are crucial for advanced computational models and difficult to achieve with physical devices or first-order emulators. The emulator is fully resistorless and offers electronic tunability via OTA bias currents, providing memductance control. The circuit was implemented using 0.18 μm CMOS technology and validated through PSPICE simulations. The results demonstrate characteristic pinched hysteresis loops (PHLs) that vary with frequency, confirming the circuit’s memristive nature. The emulator supports both incremental and decremental configurations, exhibiting robust performance under Monte Carlo and temperature variation analyses.