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<p>This paper presents a 10-bit single-channel, two-step voltage–time pipelined hybrid analog-to-digital converter (ADC) operating at a sampling rate of 2 GS/s. To simultaneously achieve high speed and high accuracy, the architecture integrates a 3-bit voltage-domain multiplying digital-to-analog converter (MDAC) with two 8-bit interleaved ping-pong time-domain ADCs (TD-ADCs), collectively forming the 10-bit resolution. In the first stage, a closed-loop, two-stage inverter-based residue amplifier (RA) is employed to ensure high linearity and fast settling, while a 1-bit redundancy is incorporated to facilitate calibration and enable dither injection. The constant-current voltage-to-time converter (CC-VTC) architecture of the TD-ADC maintains high linearity and a large input swing suitable for high-speed applications. Meanwhile, the gated ring oscillator-based time-to-digital converter (GRO-based TDC) employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. To mitigate interstage errors and improve linearity, a one-hot background calibration scheme is introduced, enabling precise gain alignment and offset correction. The prototype ADC was fabricated using a 28-nm CMOS process, occupying an active core area of 0.0301 mm<sup>2</sup>. Post-calibration measurement results demonstrate a signal-to-noise-and-distortion ratio (SNDR) of 53.20&#xa0;dB and a spurious-free dynamic range (SFDR) of 65.49&#xa0;dB at a sampling rate of 2 GS/s with the input signal at the Nyquist frequency. The total power consumption is 18.71 mW at a 1&#xa0;V supply. resulting in a Walden figure-of-merit (FoM) of 25.0 fJ/conversion step.</p>

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A 10-Bit 2-GS/s Voltage–Time-Pipelined Hybrid ADC with One-Hot Background Calibration Scoring > 60-dB SFDR in 28-nm CMOS

  • 期刊论文

  • 发表日期：

    2025年8月19日

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  • Yuan Chang,
  • Chenghao Zhang,
  • Yihang Yang,
  • Maliang Liu,
  • Yintang Yang,
  • Yong Chen

摘要

This paper presents a 10-bit single-channel, two-step voltage–time pipelined hybrid analog-to-digital converter (ADC) operating at a sampling rate of 2 GS/s. To simultaneously achieve high speed and high accuracy, the architecture integrates a 3-bit voltage-domain multiplying digital-to-analog converter (MDAC) with two 8-bit interleaved ping-pong time-domain ADCs (TD-ADCs), collectively forming the 10-bit resolution. In the first stage, a closed-loop, two-stage inverter-based residue amplifier (RA) is employed to ensure high linearity and fast settling, while a 1-bit redundancy is incorporated to facilitate calibration and enable dither injection. The constant-current voltage-to-time converter (CC-VTC) architecture of the TD-ADC maintains high linearity and a large input swing suitable for high-speed applications. Meanwhile, the gated ring oscillator-based time-to-digital converter (GRO-based TDC) employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. To mitigate interstage errors and improve linearity, a one-hot background calibration scheme is introduced, enabling precise gain alignment and offset correction. The prototype ADC was fabricated using a 28-nm CMOS process, occupying an active core area of 0.0301 mm2. Post-calibration measurement results demonstrate a signal-to-noise-and-distortion ratio (SNDR) of 53.20 dB and a spurious-free dynamic range (SFDR) of 65.49 dB at a sampling rate of 2 GS/s with the input signal at the Nyquist frequency. The total power consumption is 18.71 mW at a 1 V supply. resulting in a Walden figure-of-merit (FoM) of 25.0 fJ/conversion step.