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<p>One essential approach for calculating the Discrete Fourier Transform (DFT) is the Fast Fourier Transform (FFT), making it essential for many digital applications due to its efficiency. However, traditional FFT implementations can be complex and consume significant power, which poses challenges in the processing of digital signals, especially in power-sensitive applications. Optimizing the FFT is therefore crucial to minimize consumption of power and reduce chip area, making the technology more accessible and practical for a wide range of uses. This research focuses on addressing these challenges by proposing a Radix-4 pipelined 1024-point FFT processor. The reason for a choice of Radix 4 architecture is that it could cut down on the number of steps in the computation rather than Radix 2, hence lowering the processing time. In order to achieve further efficiency, the modified Wallace Tree (WT) multiplier is added, as the WT is popular for its low latency and good hardware utilization. This design is designed for use in biomedical signal processing, which is a field where high accuracy and efficiency are strongly needed. The system classifies the ECG signals better by leveraging the Radial Basis Function-based Convoluted Graph Neural Network (RBF-CGNN) together with the Gold Rush Optimization (GOA) algorithm. For finding complex patterns in the data, RBF-CGNN was selected, and the network parameters were optimized using GOA so that the performance was improved. The evaluations are done on MATLAB and Virtex 7 FPGA platforms that demonstrate that the suggested approach provides minimal power use and decreased chip area with high throughput. These serve as the foundation for the suggested design process and optimization techniques, which help create high-performance FFT processors appropriate for modern signal processing applications. Based on this, Radix-2 FFT Designer reduces the number of resources as well as computational procedures utilized in the execution of Radix-2 FFT designs by improving the multiplier and adder blocks. Experimental evaluations show the proposed model achieves a classification accuracy of 99.85%, with execution time reduced by up to 8.25 × compared to standard FFT implementations. Furthermore, the architecture supports real-time processing with significantly lower power usage and a maximum operating frequency of 899.3&#xa0;MHz. These improvements make the proposed design highly suitable for compact, energy-efficient biomedical devices.</p>

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Radial Basis Convoluted Graph Neural Network Based Area Efficient 1024-Point Pipelined Radix4 FFT Processer for ECG Heartbeat Categorization

  • 期刊论文

  • 发表日期：

    2025年8月26日

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  • V. Sathya,
  • M. Shakunthala,
  • V J Chakravarthy,
  • K. Radhika,
  • Gali Nageswara Rao,
  • Mahendra T. Jagtap,
  • E. Ramya,
  • Supriya Gupta Bani

摘要

One essential approach for calculating the Discrete Fourier Transform (DFT) is the Fast Fourier Transform (FFT), making it essential for many digital applications due to its efficiency. However, traditional FFT implementations can be complex and consume significant power, which poses challenges in the processing of digital signals, especially in power-sensitive applications. Optimizing the FFT is therefore crucial to minimize consumption of power and reduce chip area, making the technology more accessible and practical for a wide range of uses. This research focuses on addressing these challenges by proposing a Radix-4 pipelined 1024-point FFT processor. The reason for a choice of Radix 4 architecture is that it could cut down on the number of steps in the computation rather than Radix 2, hence lowering the processing time. In order to achieve further efficiency, the modified Wallace Tree (WT) multiplier is added, as the WT is popular for its low latency and good hardware utilization. This design is designed for use in biomedical signal processing, which is a field where high accuracy and efficiency are strongly needed. The system classifies the ECG signals better by leveraging the Radial Basis Function-based Convoluted Graph Neural Network (RBF-CGNN) together with the Gold Rush Optimization (GOA) algorithm. For finding complex patterns in the data, RBF-CGNN was selected, and the network parameters were optimized using GOA so that the performance was improved. The evaluations are done on MATLAB and Virtex 7 FPGA platforms that demonstrate that the suggested approach provides minimal power use and decreased chip area with high throughput. These serve as the foundation for the suggested design process and optimization techniques, which help create high-performance FFT processors appropriate for modern signal processing applications. Based on this, Radix-2 FFT Designer reduces the number of resources as well as computational procedures utilized in the execution of Radix-2 FFT designs by improving the multiplier and adder blocks. Experimental evaluations show the proposed model achieves a classification accuracy of 99.85%, with execution time reduced by up to 8.25 × compared to standard FFT implementations. Furthermore, the architecture supports real-time processing with significantly lower power usage and a maximum operating frequency of 899.3 MHz. These improvements make the proposed design highly suitable for compact, energy-efficient biomedical devices.