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<p>Modern real-time applications, such as multimedia and digital signal processing, frequently require floating-point (FP) arithmetic. The currently available dual-mode fused FP three-term adder supports either a single double-precision (DP) addition or two parallel single-precision (SP) additions. However, it lacks support for quadruple-precision (QP) additions, resulting in inefficient area utilization when multi-precision computations are required. To overcome this limitation, this study introduces a multi-mode fused FP three-term adder capable of performing one QP addition, two parallel DP additions, or four parallel SP additions. The proposed design also provides robust support for exceptional cases, such as zero, NaN, and infinity, and handles both normal and subnormal operations. The architecture has been implemented and evaluated on both ASIC and FPGA platforms. By enabling efficient resource sharing across the three precision modes, the proposed multi-mode design achieves lower area usage compared to existing adders, including those tailored for individual QP, dual DP, and quad SP additions, as well as configurations combining one QP unit with two dual-mode adders.</p>

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Design of Floating-Point Adder Architecture with Multi-mode Capability

  • 期刊论文

  • 发表日期：

    2025年7月31日

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  • Thiruvenkadam Krishnan,
  • Saravanan Subramanian,
  • Parthibaraj Anguraj

摘要

Modern real-time applications, such as multimedia and digital signal processing, frequently require floating-point (FP) arithmetic. The currently available dual-mode fused FP three-term adder supports either a single double-precision (DP) addition or two parallel single-precision (SP) additions. However, it lacks support for quadruple-precision (QP) additions, resulting in inefficient area utilization when multi-precision computations are required. To overcome this limitation, this study introduces a multi-mode fused FP three-term adder capable of performing one QP addition, two parallel DP additions, or four parallel SP additions. The proposed design also provides robust support for exceptional cases, such as zero, NaN, and infinity, and handles both normal and subnormal operations. The architecture has been implemented and evaluated on both ASIC and FPGA platforms. By enabling efficient resource sharing across the three precision modes, the proposed multi-mode design achieves lower area usage compared to existing adders, including those tailored for individual QP, dual DP, and quad SP additions, as well as configurations combining one QP unit with two dual-mode adders.