An 0.1 mm2/Ch 40 nm-CMOS 32-Channel Analog Front-End Acquisition Circuit with Analog-Domain Real-Time Offset Reduction and SS-ADC for LFP Neural Signal Recording
摘要
This paper presents a 32-channel analog front-end (AFE) circuit for local field potential (LFP) signal acquisition. The AFE includes 32 capacitively-coupled instrumentation amplifiers (CCIAs) with low-pass filters, and a time-division-multiplexing technique is used to save chip area by sharing a programmable gain amplifier (PGA) and a single-slope analog-to-digital converter (SS ADC) among eight recording channels. Correlated double sampling (CDS) is implemented to eliminate the offset voltage of the comparator, which can help to enhance the static characteristics of the ADC and avoid the need for offset storage capacitors. To further optimize area efficiency, the ramp generator (RAMP) and counter are shared among all 32 channels, enabling the potential for more than 32 reusable channels in future designs where higher channel integration is required. Moreover, the CCIA achieves low input-referred noise by the chopping modulation technique. To mitigate non-ideal effects induced by chopper modulation, an analog-based continuously operable offset reduction loop (ORL) is proposed. The ORL reduces the output offset caused by chopper mismatch from 116 to 1 mV (corresponding to a suppression capability of 41.3 dB) and allows DC-blocking capacitors to be placed in the loop to block the chopper ripple without increasing design complexity. The AFE circuit is simulated in 40-nm low-power (LP) CMOS technology and occupies an area of 0.1