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<p>Modern image processing applications require a low-power, efficient 2D FIR filter due to battery constraints, real-time processing, heat dissipation, resource constraints, AI integration, and cost-effectiveness. The gaps in existing works such as high computational complexity, power consumption, utilization of FPGA resources, accuracy and scalability. In this work, a Power-Area efficient Retiming-based 2D FIR Filter (PAR2DF) architecture is designed using modified Radix-4 Booth Multipliers (R4BM) and high-speed adders to overcome the challenges of the existing works. The positions of the delay registers are changed to reduce the path delay of the individual row filters of the 2D FIR Filter Architecture (FA) is called retiming. The complex multipliers are replaced by modified Booth multipliers and partial products of the multiplier are added by proposed approximate compressors and enhanced CSLA adders. These circuits balance latency, power, and area, making them ideal for real-time image processing. The individual row filter outputs are also summed by the proposed CSLA adders. The proposed 2D FIR FA design is coded by Verilog Hardware Description Language (HDL) and functional verification and synthesis have been done by the Xilinx Vivado Tool. Next, for the evaluation real cell area, path delay, and Power Consumption (PC) of the proposed filter architecture are synthesized by the Genus Synthesis tool from Cadence in 45&#xa0;nm CMOS technology. Further, the physical design is done by Innovus tools and the layout is generated. Area, delay, and power and trade-off parameters Area-Delay-Product (ADP) and Power-Delay-Product (PDP) are compared with the conventional architectures. The ADP of the proposed PAR2DF architecture has fallen by a minimum of 22.41% and PDP is reduced by a minimum of 19.84% when compared to the existing architectures. This work is validated by applying the images and filtered out. The PSNR and SSIM values are determined. Additionally, the proposed system incorporates a lightweight Machine Learning (ML) model of adaptive filtering mechanism that classifies input images based on brightness, edge density, and saturation level, enabling dynamic filter selection tailored to hazy, medical, or satellite image types.</p>

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PAR2DF: Power and Area Efficient Retiming 2D FIR Filter Architecture Using Optimized Multipliers and Adders

  • 期刊论文

  • 发表日期：

    2025年7月31日

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  • Venkata Krishna Odugu,
  • B. Janardhana Rao,
  • Gade Harish Babu

摘要

Modern image processing applications require a low-power, efficient 2D FIR filter due to battery constraints, real-time processing, heat dissipation, resource constraints, AI integration, and cost-effectiveness. The gaps in existing works such as high computational complexity, power consumption, utilization of FPGA resources, accuracy and scalability. In this work, a Power-Area efficient Retiming-based 2D FIR Filter (PAR2DF) architecture is designed using modified Radix-4 Booth Multipliers (R4BM) and high-speed adders to overcome the challenges of the existing works. The positions of the delay registers are changed to reduce the path delay of the individual row filters of the 2D FIR Filter Architecture (FA) is called retiming. The complex multipliers are replaced by modified Booth multipliers and partial products of the multiplier are added by proposed approximate compressors and enhanced CSLA adders. These circuits balance latency, power, and area, making them ideal for real-time image processing. The individual row filter outputs are also summed by the proposed CSLA adders. The proposed 2D FIR FA design is coded by Verilog Hardware Description Language (HDL) and functional verification and synthesis have been done by the Xilinx Vivado Tool. Next, for the evaluation real cell area, path delay, and Power Consumption (PC) of the proposed filter architecture are synthesized by the Genus Synthesis tool from Cadence in 45 nm CMOS technology. Further, the physical design is done by Innovus tools and the layout is generated. Area, delay, and power and trade-off parameters Area-Delay-Product (ADP) and Power-Delay-Product (PDP) are compared with the conventional architectures. The ADP of the proposed PAR2DF architecture has fallen by a minimum of 22.41% and PDP is reduced by a minimum of 19.84% when compared to the existing architectures. This work is validated by applying the images and filtered out. The PSNR and SSIM values are determined. Additionally, the proposed system incorporates a lightweight Machine Learning (ML) model of adaptive filtering mechanism that classifies input images based on brightness, edge density, and saturation level, enabling dynamic filter selection tailored to hazy, medical, or satellite image types.