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<p>In this research, a novel low-power N-bit digital comparator is proposed, demonstrating significant improvements in transistor count, power dissipation, and speed compared to existing designs. Utilizing a three-transistor EX-OR gate with optimized W/L ratios, the design effectively mitigates voltage degradation and enhances efficiency. For a 64-bit implementation, the proposed comparator uses only 1266 transistors, resulting in reductions of 20.2%, 32.4%, 62.6%, and 68.3% in transistor count compared to the designs by Piyush Tyagi, Chua et al., Lam, and Hafeez et al., respectively. It achieves a critical path delay of 0.32&#xa0;ns and a power dissipation of 49.45&#xa0;µW, representing substantial improvements of up to 99.3% in power efficiency and over 60% in speed relative to the same works. These benchmarks against well-known existing comparators confirm the superior performance of the proposed architecture. Post-layout simulations incorporating parasitic effects validate its practical applicability, and the layout is DRC and LVS verified. Enhanced performance metrics including total area and slew rate are also discussed. These advancements make the proposed comparator highly suitable for energy-efficient embedded and real-time VLSI applications.</p>

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A Novel Low-Power N-bit Comparator Design with Optimized Transistor Count for Energy-Efficient VLSI Applications

  • 期刊论文

  • 发表日期：

    2025年6月2日

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  • Jitendra Chouhan,
  • Abhay Pratap Singh,
  • R. K. Baghel

摘要

In this research, a novel low-power N-bit digital comparator is proposed, demonstrating significant improvements in transistor count, power dissipation, and speed compared to existing designs. Utilizing a three-transistor EX-OR gate with optimized W/L ratios, the design effectively mitigates voltage degradation and enhances efficiency. For a 64-bit implementation, the proposed comparator uses only 1266 transistors, resulting in reductions of 20.2%, 32.4%, 62.6%, and 68.3% in transistor count compared to the designs by Piyush Tyagi, Chua et al., Lam, and Hafeez et al., respectively. It achieves a critical path delay of 0.32 ns and a power dissipation of 49.45 µW, representing substantial improvements of up to 99.3% in power efficiency and over 60% in speed relative to the same works. These benchmarks against well-known existing comparators confirm the superior performance of the proposed architecture. Post-layout simulations incorporating parasitic effects validate its practical applicability, and the layout is DRC and LVS verified. Enhanced performance metrics including total area and slew rate are also discussed. These advancements make the proposed comparator highly suitable for energy-efficient embedded and real-time VLSI applications.