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<p>This paper introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The core components of the architecture include voltage-mode circuit for the input layer and current-mode circuits for the hidden layers and the decision making. Specifically, the main part of the architecture comprise a Gaussian function circuit, a Sigmoid function circuit, an analog multiplier, and current mirrors. A current comparator is employed as the decision-making circuit. The operational principles of the architecture are detailed and realized in an energy-efficient configuration, operating at just 865 nW with low supply rails of 0.6V. The proposed design has been tested on real-world electrical impedance tomography classification tasks, achieving a classification accuracy exceeding <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(94.22\%\)</EquationSource> </InlineEquation>. The architecture is implemented using 90nm CMOS technology and developed with the Cadence IC Suite for schematic and layout design. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the classifier. A comparative analysis of post-layout simulation results with an equivalent software-based classifier and existing literature validates the accuracy and reliable operation of the proposed architecture.</p>

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A Power and Area Efficient Analog Classifier for Electrical Impedance Tomography Applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年6月9日

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  • Vassilis Alimisis,
  • Vasileios Moustakas,
  • Konstantinos Cheliotis,
  • Christos Dimas,
  • Paul P. Sotiriadis

摘要

This paper introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The core components of the architecture include voltage-mode circuit for the input layer and current-mode circuits for the hidden layers and the decision making. Specifically, the main part of the architecture comprise a Gaussian function circuit, a Sigmoid function circuit, an analog multiplier, and current mirrors. A current comparator is employed as the decision-making circuit. The operational principles of the architecture are detailed and realized in an energy-efficient configuration, operating at just 865 nW with low supply rails of 0.6V. The proposed design has been tested on real-world electrical impedance tomography classification tasks, achieving a classification accuracy exceeding \(94.22\%\) . The architecture is implemented using 90nm CMOS technology and developed with the Cadence IC Suite for schematic and layout design. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the classifier. A comparative analysis of post-layout simulation results with an equivalent software-based classifier and existing literature validates the accuracy and reliable operation of the proposed architecture.