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<p>In this approach, we propose a novel analog weighted mean filter (WMF) front end for de-noising corrupted images. The proposed WMF frontend estimates the mean of analog voltages from pixels in a 3 × 3 kernel of the input image to replace the corrupted processing pixel (PP). The methodology of the proposed WMF is to employ a MOS transconductance pair for each input pixel. The design methodology incorporates linearization of MOSFET outputs for a change in input and a constant feature size to tail current ratio. The weight values of the filter mask are accomplished by proportional bias current at the tail of the corresponding differential pair. The positive terminal (PT) and the negative terminal (NT) of the nine differential pairs are shorted separately, and the net differential voltage across PT-NT of the cascaded circuit gives the weighted mean value that is used to replace PP. The schematic of the WMF is designed using 180&#xa0;nm Semi-Conductor Laboratory CMOS fabrication technology with 1.8&#xa0;V MOSFETs for implementation. The significance of the reported analog frontend is the very low silicon area on the hardware and minimal power dissipation. The functional efficiency of the proposed WMF is assessed through simulations with various sets of test signals. Evaluations reveal that the suggested WMF can achieve 54× area reduction and 26× delay reduction compared to the best of its similar digital counterpart with implementation in the same ASIC PDK node.</p>

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ASIC Design of Analog Weighted Mean Filter Frontend for Image Processing Application

  • 期刊论文

  • 发表日期：

    2025年5月28日

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  • K. N. Vijeyakumar,
  • D. Silambarasan,
  • Talluri Vineel Jessy,
  • N. Saravanakumar,
  • M. Manjubala

摘要

In this approach, we propose a novel analog weighted mean filter (WMF) front end for de-noising corrupted images. The proposed WMF frontend estimates the mean of analog voltages from pixels in a 3 × 3 kernel of the input image to replace the corrupted processing pixel (PP). The methodology of the proposed WMF is to employ a MOS transconductance pair for each input pixel. The design methodology incorporates linearization of MOSFET outputs for a change in input and a constant feature size to tail current ratio. The weight values of the filter mask are accomplished by proportional bias current at the tail of the corresponding differential pair. The positive terminal (PT) and the negative terminal (NT) of the nine differential pairs are shorted separately, and the net differential voltage across PT-NT of the cascaded circuit gives the weighted mean value that is used to replace PP. The schematic of the WMF is designed using 180 nm Semi-Conductor Laboratory CMOS fabrication technology with 1.8 V MOSFETs for implementation. The significance of the reported analog frontend is the very low silicon area on the hardware and minimal power dissipation. The functional efficiency of the proposed WMF is assessed through simulations with various sets of test signals. Evaluations reveal that the suggested WMF can achieve 54× area reduction and 26× delay reduction compared to the best of its similar digital counterpart with implementation in the same ASIC PDK node.