This article unveils the impact of multiple work function metal gate in Strain Channel Double Gate (SCDG) junction-less Transistor (JLT) in the sub-20nm regime for Power-speed efficient VLSI application with negligible Short Channel Effects (SCEs). Sentaurus TCAD is used on which the 14nm design and two-dimensional simulation of Conventional Double Gate (DG) JLT, SCDG JLT and Work Function Tuning (WFT) with SCDG JLT are executed at 0.8V supply. The strain-Si in Conventional DG JLT offers 7.8% better ON current due to the mobility enhancement, thus results in 11.3x higher leakage and 34% roll-off of threshold voltage ( \(\hbox {V}_{{TH}}\) ). The main objective of this work is to improve the subthreshold performance of the prementioned SCDG JLT, which is addressed by incorporating WFT. This results in improving the leakage and \(\hbox {V}_{{TH}}\) roll-off without disturbing the performance in the ON stage. Once the metrics like \(\hbox {I}_{{ON}}\) / \(\hbox {I}_{{OFF}}\) ratio, Subthreshold Slope (SS), \(\hbox {V}_{{TH}}\) and Transconductance ( \(\hbox {G}_{{M}}\) ) are analyzed, the proposed devices are validated by configuring a few circuits such as inverter, inverter chain, ring oscillator (RO) and SRAM. WFT has made the inverter to provide lesser delay, wider noise margin, and steep voltage transfer characteristics. Accordingly, its 3-stage inverter chain and RO arrangement offered smaller power consumption and quick response time. The RO with WFT is also found to generate comparatively higher frequency amongst the three devices. Also, the WFT based 6T SRAM offers better static noise margin as calculated from the butterfly curve for read, write and hold operation.
