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<p>Designing bio-implantable receivers, especially battery-powered RF receivers with strict energy limitations, requires the use of low leakage transistors. Reducing energy dissipation caused by leakage is a major focus in microelectronics circuits. The miniaturization of MOS transistors has worsened the problem of leakage power in VLSI circuits. Several methods have been suggested to reduce leakage power in CMOS circuits, including modifying the threshold voltage, integrating sleep transistors, and enhancing route resistances. Nevertheless, these techniques generally necessitate the inclusion of two more transistors, leading to an enlarged layout area and a longer time for signals to propagate. Additionally, some of these solutions experience reduced voltage fluctuations at the output. This work presents an innovative method for managing leakage in CMOS circuits by incorporating just one more transistor. The suggested method has undergone evaluation on universal gates and benchmark circuits, demonstrating greater performance in comparison to existing techniques. The sizing of the additional transistor has been done by well known gm/Id method. The simulation findings demonstrate enhancements of up to 31.88% in reducing leakage power, 26.21% in reducing propagation delay, 10.54% in reducing power-delay product, and 17.88% in reducing layout area. The improvements are accomplished by utilizing Cadence Virtuoso tools in 90-nm technology, which makes the method extremely appropriate for bio-implantable receivers with ultra-low power requirements.</p>

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Single Transistor Leakage Control for Low Power CMOS Circuits in Bio-implantable RF Receivers

  • 期刊论文

  • 发表日期：

    2025年5月7日

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  • Shubhankar Majumdar

摘要

Designing bio-implantable receivers, especially battery-powered RF receivers with strict energy limitations, requires the use of low leakage transistors. Reducing energy dissipation caused by leakage is a major focus in microelectronics circuits. The miniaturization of MOS transistors has worsened the problem of leakage power in VLSI circuits. Several methods have been suggested to reduce leakage power in CMOS circuits, including modifying the threshold voltage, integrating sleep transistors, and enhancing route resistances. Nevertheless, these techniques generally necessitate the inclusion of two more transistors, leading to an enlarged layout area and a longer time for signals to propagate. Additionally, some of these solutions experience reduced voltage fluctuations at the output. This work presents an innovative method for managing leakage in CMOS circuits by incorporating just one more transistor. The suggested method has undergone evaluation on universal gates and benchmark circuits, demonstrating greater performance in comparison to existing techniques. The sizing of the additional transistor has been done by well known gm/Id method. The simulation findings demonstrate enhancements of up to 31.88% in reducing leakage power, 26.21% in reducing propagation delay, 10.54% in reducing power-delay product, and 17.88% in reducing layout area. The improvements are accomplished by utilizing Cadence Virtuoso tools in 90-nm technology, which makes the method extremely appropriate for bio-implantable receivers with ultra-low power requirements.