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<p>This paper presents a continuous-time incremental sigma-delta ADC with an extended counting technique for photocurrent readout. Detailed analysis of continuous time extended counting technique indicates the necessity of zero-order hold equivalent digital filter and time constant calibration. An auto-tuning technique is then proposed to calibrate RC time constant variations under different PVT conditions. Besides, to compensate for gain errors in the proposed two-step ADC, half of each input pair in the comparator of SAR ADC is swapped after sampling. The continuous time extended-counting ADC is fabricated in a 0.18&#xa0;μm CMOS process and occupies an active area of 0.66 mm<sup>2</sup>. The power consumption is 103.1&#xa0;μW under a 1.8&#xa0;V supply. The measured SNR/SNDR/DR is 82.6 dB/82.5 dB/86.1 dB over a bandwidth of 3.9 kHz, respectively.</p>

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A Continuous-Time Incremental ΣΔ ADC with Extended Counting Technique

  • 期刊论文

  • 发表日期：

    2025年3月21日

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  • Tingting Wei,
  • Zhu Yuan,
  • Qiong Wang,
  • Xiaoyang Zeng

摘要

This paper presents a continuous-time incremental sigma-delta ADC with an extended counting technique for photocurrent readout. Detailed analysis of continuous time extended counting technique indicates the necessity of zero-order hold equivalent digital filter and time constant calibration. An auto-tuning technique is then proposed to calibrate RC time constant variations under different PVT conditions. Besides, to compensate for gain errors in the proposed two-step ADC, half of each input pair in the comparator of SAR ADC is swapped after sampling. The continuous time extended-counting ADC is fabricated in a 0.18 μm CMOS process and occupies an active area of 0.66 mm2. The power consumption is 103.1 μW under a 1.8 V supply. The measured SNR/SNDR/DR is 82.6 dB/82.5 dB/86.1 dB over a bandwidth of 3.9 kHz, respectively.