This paper presents the design and analysis of a high-speed rail-to-rail clocked comparator implemented using the 65-nm CMOS process. The proposed comparator improves the conventional design by enhancing transconductance across the rail-to-rail common mode range. By connecting input transistors in parallel, the latch circuit is directly linked to the tail transistor, resulting in improved \(t_o\) and \(t_{latch}\) delay. Additionally, efficiency in operation at lower supply voltages is achieved through reduced transistor stacking. The comparative analysis with the proposed comparator demonstrates a substantial increase in the clock frequency, with the proposed design operating at 7 GHz while the conventional comparator is 2 GHz. Furthermore, the proposed comparator exhibits superior energy efficiency per conversion across the entire common mode range due to increased frequency and using a single-tail transistor. Performance evaluation reveals a significant reduction in delay and offset voltage compared to conventional design. The delay of the conventional and proposed comparators are 215 ps and 52 ps, respectively. Moreover, the proposed comparator demonstrates a kickback noise of 1.7 mV at 500 mV common mode voltage. The proposed comparator gives 100% yield at 11.8 mV differential voltage over the entire common mode range, while for the conventional comparator gives at 16 mV. The proposed rail-to-rail clocked comparator is tested as a sense amplifier in memory applications. It reduces the read time of SRAM by 98%. In DRAM, the refresh frequency during hold time is reduced by 98% compared to the original refresh time.
