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<p>The advent of the graphene nanoribbon field effect transistor (GNRFET) facilitates the design of digital circuits based on multi-valued logic. This is attributed to the transistor’s capability to adjust the threshold voltage by modifying width of graphene nanoribbon. This paper aims to design and evaluate new 1-trit and 2-trit multiplier cells using ternary logic and 32-nm GNRFETs. The suggested designs’ efficiency is compared with the recently published circuits at the presence of process-voltage-temperature (PVT) variations. The results obtained from HSPICE simulations demonstrate that our 1-trit ternary multiplier exhibits an 11.92% and 22.64% reduction in delay compared to Abbasian’s and Rohani’s designs, respectively. Furthermore, it achieves a decrease in power consumption (energy consumption) of at least 20.39% (46.25%), compared to the best design, that is Abbasian’s design. Additionally, it requires the use of one less transistor compared to the most favorable design explored. Moreover, it demonstrates greater reliability against PVT variations. Nonetheless, when compared to Sudhakar’s and Wang’s designs, the suggested circuit exhibits a delay increase of 1.1 and 1.57 times, respectively. On the other hand, the proposed 2-trit ternary multiplier offers a power (energy) improvement of at least 6.86% (16.67%), compared to the top-performance design.</p>

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High Performance and PVT Variation Tolerant Design for a Ternary Multiplier Using GNRFET Technology

  • 期刊论文

  • 发表日期：

    2025年3月11日

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  • Shaik Javid Basha,
  • Ahmed Elbarbary,
  • Haitham A. Mahmoud,
  • P. Venkatramana

摘要

The advent of the graphene nanoribbon field effect transistor (GNRFET) facilitates the design of digital circuits based on multi-valued logic. This is attributed to the transistor’s capability to adjust the threshold voltage by modifying width of graphene nanoribbon. This paper aims to design and evaluate new 1-trit and 2-trit multiplier cells using ternary logic and 32-nm GNRFETs. The suggested designs’ efficiency is compared with the recently published circuits at the presence of process-voltage-temperature (PVT) variations. The results obtained from HSPICE simulations demonstrate that our 1-trit ternary multiplier exhibits an 11.92% and 22.64% reduction in delay compared to Abbasian’s and Rohani’s designs, respectively. Furthermore, it achieves a decrease in power consumption (energy consumption) of at least 20.39% (46.25%), compared to the best design, that is Abbasian’s design. Additionally, it requires the use of one less transistor compared to the most favorable design explored. Moreover, it demonstrates greater reliability against PVT variations. Nonetheless, when compared to Sudhakar’s and Wang’s designs, the suggested circuit exhibits a delay increase of 1.1 and 1.57 times, respectively. On the other hand, the proposed 2-trit ternary multiplier offers a power (energy) improvement of at least 6.86% (16.67%), compared to the top-performance design.