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<p>Due to the irrational coefficients, the orthogonal wavelet filter banks (FBs) need a lot of resources when implemented on hardware. As a result, there is a decrease in operating speed, a significant memory requirement, and an increase in power consumption. This paper proposes an orthogonal low complex symmetric Daubechies-2 (4-tap) wavelet filter bank (FB) to address these problems. This is accomplished by obtaining dyadic filter coefficients and making the suggested FB symmetric by marginally modifying the perfect reconstruction (PR) criterion. By using fewer adders and shifters, the suggested wavelet FB achieves a significant reduction in dynamic power consumption without the need for multipliers. This is confirmed by implementing the suggested wavelet FB on the Zedboard ZYNQ-7000 AP-SoC (Zynq FPGA from Xilinx) field programmable gate array (FPGA). The suitability of the suggested FB is tested in medical image retrieval and image compression applications. Results from simulations demonstrate that, when compared to state-of-the-art techniques, the suggested wavelet FB performs better in terms of retrieval accuracy (ARP, ARR) for medical image retrieval and PSNR for image compression on the benchmark image datasets.</p>

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A New Design and VLSI Implementation of Symmetric Daubechies Wavelet Filter Bank for Image Processing Applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年1月17日

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  • Aswini K. Samantaray,
  • Amol D. Rahulkar,
  • Satyajeet Sahoo,
  • Pradeep Gorre

摘要

Due to the irrational coefficients, the orthogonal wavelet filter banks (FBs) need a lot of resources when implemented on hardware. As a result, there is a decrease in operating speed, a significant memory requirement, and an increase in power consumption. This paper proposes an orthogonal low complex symmetric Daubechies-2 (4-tap) wavelet filter bank (FB) to address these problems. This is accomplished by obtaining dyadic filter coefficients and making the suggested FB symmetric by marginally modifying the perfect reconstruction (PR) criterion. By using fewer adders and shifters, the suggested wavelet FB achieves a significant reduction in dynamic power consumption without the need for multipliers. This is confirmed by implementing the suggested wavelet FB on the Zedboard ZYNQ-7000 AP-SoC (Zynq FPGA from Xilinx) field programmable gate array (FPGA). The suitability of the suggested FB is tested in medical image retrieval and image compression applications. Results from simulations demonstrate that, when compared to state-of-the-art techniques, the suggested wavelet FB performs better in terms of retrieval accuracy (ARP, ARR) for medical image retrieval and PSNR for image compression on the benchmark image datasets.