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<p>Traditionally, the precision of noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) is limited by the linearity of open-loop residue amplifier and it is challenging to achieve high-order (≥ 3) noise-shaping. To mitigate aforementioned limitations, we innovatively propose a fourth-order NS SAR ADC, which adopts the 2–2 hybrid nested (HN) structure that nests error feedback (EF) and cascaded integrator feed-forward (CIFF). With the aid of the 2–2 HN structure, a process-voltage-temperature (PVT)-robust high-order noise-shaping has been successfully implemented in NS SAR ADC. Moreover, to achieve high precision: (1) The closed-loop cascode floating inverter amplifier (FIA) is employed as residue amplifier, breaking the tradeoff between linearity of dynamic amplifier and high precision while maintaining high power efficiency, and realizing a truly high-precision NS SAR ADC with PVT robustness. (2) Sampling KT/C noise cancellation (SNC) technique is exploited to reduce the size of capacitive digital-to-analog converter (CDAC) while meeting the same precision requirements. The proposed ADC was prototyped in a 55&#xa0;nm CMOS process, achieving a high-precision signal-to-noise-and-distortion ratio (SNDR) of 92.6&#xa0;dB, capable of maintaining SNDR exceeding 90&#xa0;dB across PVT variations. It operates within a 312.5&#xa0;kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, consuming 272&#xa0;μW power under 1.2&#xa0;V supply and realizing a Schreier figure of merit (FoMs) of 183&#xa0;dB.</p>

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A 92 dB SNDR 183 dB FoMs Fully Dynamic Fourth-Order Noise-Shaping SAR ADC in the 2–2 Hybrid Nested Structure with Closed-Loop Residue Amplifier

  • 期刊论文

  • 发表日期：

    2025年2月9日

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  • Wei Hu,
  • Jiaqi Li,
  • Qunchao Chen

摘要

Traditionally, the precision of noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) is limited by the linearity of open-loop residue amplifier and it is challenging to achieve high-order (≥ 3) noise-shaping. To mitigate aforementioned limitations, we innovatively propose a fourth-order NS SAR ADC, which adopts the 2–2 hybrid nested (HN) structure that nests error feedback (EF) and cascaded integrator feed-forward (CIFF). With the aid of the 2–2 HN structure, a process-voltage-temperature (PVT)-robust high-order noise-shaping has been successfully implemented in NS SAR ADC. Moreover, to achieve high precision: (1) The closed-loop cascode floating inverter amplifier (FIA) is employed as residue amplifier, breaking the tradeoff between linearity of dynamic amplifier and high precision while maintaining high power efficiency, and realizing a truly high-precision NS SAR ADC with PVT robustness. (2) Sampling KT/C noise cancellation (SNC) technique is exploited to reduce the size of capacitive digital-to-analog converter (CDAC) while meeting the same precision requirements. The proposed ADC was prototyped in a 55 nm CMOS process, achieving a high-precision signal-to-noise-and-distortion ratio (SNDR) of 92.6 dB, capable of maintaining SNDR exceeding 90 dB across PVT variations. It operates within a 312.5 kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, consuming 272 μW power under 1.2 V supply and realizing a Schreier figure of merit (FoMs) of 183 dB.