Low Cost and High Throughput VLSI Architectures of Folded and Parallel Sorters

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发表日期：

2024年12月31日

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M. Mohamed Asan Basiri

摘要

The modern engineering applications such as digital signal processing, high performance computing, data science, and so on often require the operation of sorting. This article proposes efficient folded architectures I, II, and III along with the efficient parallel architectures I and II for the sorting. Here, the folded architecture - I, folded architecture - II, parallel architecture - I, and parallel architecture - II are used to sort a sequence with two bitonic halfs. In the proposed folded architectures, the optimizations on the area and power are achieved. In the proposed parallel architectures, more numbers of sorting operations are done in parallel to improve the throughput. All the existing and proposed designs are implemented in 45 nm CMOS technology with Cadence ASIC design tool. The proposed parallel architecture - I of sorting of length 16 achieves $93\%$ $93 %$ of improvement in throughput as compared with the conventional bitonic architecture. The proposed folded architecture - II of sorting of length 16 achieves $89\%$ $89 %$ of reduction in area as compared with the conventional bitonic architecture.